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SN74LV11ADR_TI(德州仪器)中文资料_英文资料_价格_PDF手册

2024/5/6 17:37:34

6

SN74LV11ADR

3 通道、3 输入、2V 至 5.5V 与门



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· 2-V to 5.5-V VCC Operation 

· Max tpd of 7 ns at 5 V 

· Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C

· Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C

· Support Mixed-Mode Voltage Operation on All Ports 

· Ioff Supports Partial-Power-Down Mode Operation 

· Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II 

· ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

 

 

                                                   

 

description/ordering information

 

These triple 3-input positive-AND gates are designed for 2-V to 5.5-V VCC operation.

 

The LV11A devices perform the Boolean function Y= A • B • C or Y=A B C in positive logic.

 

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.