芯云购商城
搜索关键词不能为空
搜索关键词不能为空
收缩

QQ在线咨询

电话咨询

  • 0755-82579613

Skype 咨询

  • 3003361628@qq.com

SN74F112NSRG4_TI(德州仪器)中文资料_英文资料_价格_PDF手册

2024/4/2 9:37:42

315


SN74F112NSRG4

具有清零和预置端的双路负边沿触发式 J-K 触发器

 

 

                                      更多技术详情请登录www.mroic.cn          

 

 

• Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

 

 

                                                           


 

Description

 

The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high.

 

The SN74F112 is characterized for operation from 0°C to 70°C.