2024/4/2 14:10:51
621
· 2-V to 6-V VCC Operation
· Inputs Accept Voltages to 6 V
· Max tpd of 10 ns at 5 V
description/ordering information
The ’AC74 devices are dual positive-edgetriggered D-type flip-flop
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.
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20万现货SKU
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科技智能大仓储
4小时快速交货
仅从原厂和代理商进货
每一颗料均可原厂追溯
明码标价节省时间成本
一站式采购正品元器件
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