2023/10/16 15:55:45
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1 Features
? Ultra-Low Noise, High Performance
– Jitter: 90 fs RMS Typical fOUT > 100 MHz
– PSRR: –70 dBc, Robust Supply Noise Immunity
? Flexible Output Format; User Selectable
– LVPECL up to 1 GHz
– LVDS up to 900 MHz
– HCSL up to 400 MHz
? Total Frequency Tolerance of ±50 ppm
? System Level Features
– Frequency Margining: Fine and Coarse
– Internal EEPROM: User Configurable Default Settings
? Other Features
– Device Control: I 2C
– 3.3-V Operating Voltage
– Industrial Temperature Range (–40oC to 85oC)
– 7-mm × 5-mm 8-Pin Package
– Create a Custom Design Using the LMK61E2 With the WEBENCH? Power Designer
2 Applications
? High-Performance Replacement for Crystal-, SAW-, or Silicon-Based Oscillators
? Switches, Routers, Network Line Cards, Base Band Units (BBU), Servers, Storage/SAN
? Test and Measurement
? Medical Imaging
? FPGA, Processor Attach
3 Description
The LMK61E2 device is an ultra-low jitter PLLatinum? programmable oscillator with a fractional-N frequency synthesizer with integrated VCO that generates commonly used reference clocks. The outputs can be configured as LVPECL, LVDS, or HCSL.
The device features self start-up from on-chip EEPROM that is factory programmed to generate 156.25-MHz LVPECL output. The device registers and EEPROM settings are fully programmable insystem through I 2C serial interface. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3-V ± 5% supply.
The device provides fine and coarse frequency margining options through I 2C serial interface to support system design verification tests (DVT), such as standard compliance and system timing margin testing.
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20万现货SKU
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科技智能大仓储
4小时快速交货
仅从原厂和代理商进货
每一颗料均可原厂追溯
明码标价节省时间成本
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