ADS7824U/1K

4 通道、12 位采样 CMOS 模数转换器

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FEATURES

● 25μs max SAMPLING AND CONVERSION

● SINGLE 5V SUPPLY OPERATION

● PIN-COMPATIBLE WITH 16-BIT ADS7825

● PARALLEL AND SERIAL DATA OUTPUT

● 28-PIN 0.3" PLASTIC DIP AND SOIC

● ±0.5 LSB max INL AND DNL

● 50mW max POWER DISSIPATION

● 50μW POWER DOWN MODE

● ±10V INPUT RANGE, FOUR CHANNEL MULTIPLEXER

● CONTINUOUS CONVERSION MODE

DESCRIPTION

The ADS7824 can acquire and convert 12 bits to within ±0.5 LSB in 25μs max while consuming only 50mW max. Laser-trimmed scaling resistors provide the standard industrial ±10V input range and channelto-channel matching of ±0.1%. The ADS7824 is a low-power 12-bit sampling A/D with a four channel input multiplexer, S/H, clock, reference, and a parallel/serial microprocessor interface. It can be configured in a continuous conversion mode to sequentially digitize all four channels. The 28-pin ADS7824 is available in a plastic 0.3" DIP and in a SOIC, both fully specified for operation over the industrial –40°C to 85°C range.

BASIC OPERATION

PARALLEL OUTPUT

Figure 1a shows a basic circuit to operate the ADS7824 with parallel output (Channel 0 selected). Taking R/C (pin 22) LOW for 40ns (12μs max) will initiate a conversion. BUSY (pin 24) will go LOW and stay LOW until the conversion is completed and the output register is updated. If BYTE (pin 21) is LOW, the 8 most significant bits will be valid when pin 24 rises; if BYTE is HIGH, the 4 least significant bits will be valid when BUSY rises. Data will be output in Binary Two’s Complement format. BUSY going HIGH can be used to latch the data. After the first byte has been read, BYTE can be toggled allowing the remaining byte to be read. All convert commands will be ignored while BUSY is LOW.

The ADS7824 will begin tracking the input signal at the end of the conversion. Allowing 25μs between convert commands assures accurate acquisition of a new signal.

SERIAL OUTPUT

Figure 1b shows a basic circuit to operate the ADS7824 with serial output (Channel 0 selected). Taking R/C (pin 22) LOW for 40ns (12μs max) will initiate a conversion and output valid data from the previous conversion on SDATA (pin 16) synchronized to 12 clock pulses output on DATACLK (pin 15). BUSY (pin 24) will go LOW and stay LOW until the conversion is completed and the serial data has been transmitted. Data will be output in Binary Two’s Complement format, MSB first, and will be valid on both the rising and falling edges of the data clock. BUSY going HIGH can be used to latch the data. All convert commands will be ignored while BUSY is LOW.

The ADS7824 will begin tracking the input signal at the end of the conversion. Allowing 25μs between convert commands assures accurate acquisition of a new signal.