2024/7/13 16:31:00
60
· Inputs Are TTL-Voltage Compatible
· Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
· Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception
· Latch-Up Performance Exceeds 250 mA Per JESD 17
· ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
The ’AHCT138 3-line to 8-line decoders/demultiplexers are designed to be used in high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
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